GS8320Z36AGT-200 SRAM 2.5 or 3.3V 1M x 36 36M Integrated Circuits ICs
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Integrated Circuits ICs
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Specifications
Date Code:
Newest Code
Shipping By:
DHL/UPS/Fedex
Condition:
New*Original
Warranty:
365days
Lead Free:
Rohs Compliant
Lead Times:
Immediately Shipment
Package:
BGA-165
Mounting Style:
SMD/SMT
Introduction
GS8320Z36AGT-200 SRAM 2.5 or 3.3V 1M x 36 36M
| GSI Technology | |
| Product Category: | SRAM |
| RoHS: | Details |
| 36 Mbit | |
| 1 M x 36 | |
| 6.5 ns | |
| 200 MHz | |
| Parallel | |
| 3.6 V | |
| 2.3 V | |
| 205 mA, 240 mA | |
| 0 C | |
| + 70 C | |
| SMD/SMT | |
| TQFP-100 | |
| Tray | |
| Brand: | GSI Technology |
| Memory Type: | SDR |
| Moisture Sensitive: | Yes |
| Product Type: | SRAM |
| Series: | GS8320Z36AGT |
| 18 | |
| Subcategory: | Memory & Data Storage |
| Tradename: | NBT SRAM |
| Type: | NBT Pipeline/Flow Through |
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The GS8320Z36AGT is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth
by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a
synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock.
Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode
enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and
turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off chip write pulse generation required by asynchronous SRAMs and simplifies
input signal timing. The GS8320Z36AGT may be configured by the user to operate in Pipeline or Flow Through mode.
Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input
signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily
stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising
edge of clock. The GS8320Z36AGT is implemented with GSI's high performance CMOS technology and is available in a
JEDECstandard 100-pin TQFP package.
Key Features
- NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both
- pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- User-configurable Pipeline and Flow Through mode
- LBO pin for Linear or Interleave Burst mode
- Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
- Byte write operation (9-bit Bytes)
- 3 chip enable signals for easy depth expansion
- ZZ Pin for automatic power-down
- RoHS-compliant 100-lead TQFP package available
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Stock:
MOQ:
1pcs
