EP2S30F672I5N Enhanced Configuration (EPC) Devices Integrated Circuits ICs
Category:
Integrated Circuits ICs
Price:
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Specifications
Date Code:
Newest Code
Shipping By:
DHL/UPS/Fedex
Condition:
New*Original
Warranty:
365days
Lead Free:
Rohs Compliant
Lead Times:
Immediately Shipment
Package:
FBGA672
Mounting Style:
SMD/SMT
Introduction
EP2S30F672I5N Enhanced Configuration (EPC) Devices Integrated Circuits ICs
| Altera | |
| Product Category: | Enhanced Configuration Devices |
| RoHS: | Details |
| SMD/SMT | |
| FBGA672 | |
| Brand: | Texas Instruments |
| Product: | Enhanced Configuration Devices |
| Product Type: | Enhanced Configuration Devices |
| Subcategory: | PMIC - Power Management ICs |
| Type: | Enhanced Configuration Devices |
| Unit Weight: | 0.001270 oz |
FeaturesEPC devices offer the following features:
■ Single-chip configuration solution for Altera ACEX 1K, APEX 20K (includingAPEX 20K, APEX 20KC,
and APEX 20KE), APEX II, Arria GX, Cyclone,Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA),
Mercury,Stratix II, and Stratix II GX devices
■ Contains 4-, 8-, and 16-Mb flash memories for configuration data storage
■ On-chip decompression feature almost doubles the effective configurationdensity■ Standard flash die and a
controller die combined into single stacked chip package
■ External flash interface supports parallel programming of flash and externalprocessor access to unused
portions of memory
■ Flash memory block or sector protection capability using the external flashinterface
■ Supported in EPC4 and EPC16 devices
■ Page mode support for remote and local reconfiguration with up to eightconfigurations for the entire system
■ Compatible with Stratix series remote system configuration feature■ Supports byte-wide configuration mode
fast passive parallel (FPP) with an 8-bitdata output per DCLK cycle
■ Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
Pin selectable 2-ms or 100-ms power-on reset (POR) time
■ Configuration clock supports programmable input source and frequency synthesis
■ Multiple configuration clock sources supported (internal oscillator andexternal clock input pin)
■ External clock source with frequencies up to 100 MHz■ Internal oscillator defaults to 10 MHz and you can
program the internaloscillator for higher frequencies of 33, 50, and 66 MHz
■ Clock synthesis supported using user programmable divide counter
■ Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin UltraFineLine BGA (UFBGA) packages
■ Vertical migration between all devices supported in the 100-pin PQFP package
■ Supply voltage of 3.3 V (core and I/O)
■ Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)specification■ Supports ISP
using Jam Standard Test and Programming Language (STAPL)
■ Supports JTAG boundary scan
■ The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
■ Internal pull-up resistor on the nINIT_CONF pin always enabled
■ User programmable weak internal pull-up resistors on nCS and OE pins
■ Internal weak pull-up resistors on external flash interface address and controllines, bus hold on data lines
■ Standby mode with reduced power consumption
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Stock:
MOQ:
1pcs
