8T49N241-031NLGI FemtoClock NG Universal Frequency Translator Integrated Circuits ICs
8T49N241-031NLGI FemtoClock NG Universal Frequency Translator Integrated Circuits ICs
| IDT | |
| Product Category: | Frequency Translator |
| RoHS: | Details |
| VFQFN | |
| Standard | |
| Brand: | IDT |
| Subcategory: | Integrated Circuits ICs |
| Type: | JFET |
| Unit Weight: | -oz |
General Description
The 8T49N241 has one fractional-feedback PLL that can be used as a jitter attenuator and frequency trans1ator.
It is equipped with one integer and three fractional output dividers, allowing the generation of up to four different
output frequencies, ranging from 8kHz to 1GHz.
These frequencies are completely independent of each other, the input reference frequencies and the crystal
reference frequency. The device places virtually no constraints on input to output frequency conversion.
supporting all FEC rates. including the new revision of . ITU-T Recommendation G.709 (2009). most with
0ppm conversion error. The outputs may select among LVPECL. LVDS, HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,including 1G, 10G, 40G and 100G
Synchronous Ethernet, OIN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N241 accepts up to two differentia1 or single-ended input clocks and a fundamenta1-mode crystal
input. The interna1 PLL can lock to either of the input reference clocks or just to the crysta1 to behave as a
frequency synthesizer. The PLL can use the second input for redundant backup of the primary input reference,
but in this case, both input clock references must be related in frequency.
The device supports hitless reference switching between input clocks. The device monitors both input clocks
for Loss of Signal(LOS), and generates an alarm when an input clock failure is detected. Automatic and
manual hit1ess reference switching options are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N241 supports holdover. The holdover has an initial accuracy of +50ppB from the point where
the loss of all applicable input reference(s) has been detected. It maintains a historical .
average operating point for the PLL that may be returned to in holdover at a 1imited phase slope.
The PLL has a register-selectable 1oop bandwidth from 0.2Hz to 6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also supports I2C master capability to allow the
register configuration to be read from an external EEPROM. Programming with IDT's Timing Commander
software is recommended for optimal device performance. Factory pre-programmed devices are also availab1e.
Applications
●OTN or SONET 1 SDH equipment
●Gigabit and Terabit IP switches 1 routers including Synchronous
Ethernet
●Video broadcast
