CY7C1360S-166AXC SRAM 9Mb 166Mhz 256K x 36 Pipelined SRAM Integrated Circuits ICs
CY7C1360S-166AXC SRAM 9Mb 166Mhz 256K x 36 Pipelined SRAM
| CYPRESS | |
| Product Category: | SRAM |
| RoHS: | Details |
| 9 Mbit | |
| 256 k x 36 | |
| 3.5 ns | |
| 166 MHz | |
| Parallel | |
| 3.6 V | |
| 3.135 V | |
| 0 C | |
| + 70 C | |
| SMD/SMT | |
| LQFP-100 | |
| Tray | |
| Brand: | CYPRESS |
| Memory Type: | SDR |
| Moisture Sensitive: | Yes |
| Product Type: | SRAM |
| Series: | CY7C1360S |
| Subcategory: | Memory & Data Storage |
Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs
include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables
(CE2and CE3), Burst Control inputs (ADSC, ADSP, andADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor
(ADSP) of Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally
generated as controlled by the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part
supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can
be one to two or four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes
all bytes to be written.
The CY7C1360B/CY7C1362B operates from a +3.3V core power supply while all cutputs may operate with
either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in Lead-Free 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
