CY7C1411KV18-250BZXC SRAM - Synchronous QDR II Memory IC 36Mbit Parallel 250 MHz ICS

CY7C1411KV18-250BZXC SRAM - Synchronous QDR II Memory IC 36Mbit Parallel

250 MHz ICS

DESCRIPTION

The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, andCY7C1415KV18 are 1.8 V synchronous

pipelined SRAMs,equipped with QDR II architecture. QDR II architecture consistsof two separate ports:

the read port and the write port to accessthe memory array. The read port has dedicated data outputs

tosupport read operations and the write port has dedicated datainputs to support write operations.

QDR II architecture hasseparate data inputs and data outputs to completely eliminatethe need to

“turnaround” the data bus that exists with commonI/O devices. Each port can be accessed through a

commonaddress bus. Addresses for read and write addresses arelatched on alternate rising edges of

the input (K) clock. Accessesto the QDR II read and write ports are independent of oneanother.

To maximize data throughput, both read and write portsare equipped with DDR interfaces. Each address

location isassociated with four 8-bit words (CY7C1411KV18), 9-bit words(CY7C1426KV18), 18-bit words

(CY7C1413KV18), or 36-bitwords (CY7C1415KV18) that burst sequentially into or out of thedevice.

Because data can be transferred into and out of thedevice on every rising edge of both input clocks

(K and K and Cand C), memory bandwidth is maximized while simplifyingsystem design by eliminating

bus ‘turnarounds’.Depth expansion is accomplished with port selects, whichenables each port to operate

independently.All synchronous inputs pass through input registers controlled bythe K or K input clocks.

All data outputs pass through outputregisters controlled by the C or C (or K or K in a single clockdomain)

input clocks. Writes are conducted with on-chipsynchronous self-timed write circuitry.

Features

■ Separate independent read and write data ports

   ❐ Supports concurrent transactions

■ 333 MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) Interfaces on both read and write ports(data transferred at 666 MHz) at 333 MHz

■ Two input clocks (K and K) for precise DDR timing

   ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clockskew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speedsystems

■ Single multiplexed address input bus latches address inputsfor read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR® II operates with 1.5 cycle read latency when DOFF isasserted HIGH

■ Operates similar to QDR I device with 1 cycle read latency whenDOFF is asserted LOW

■ Available in × 8, × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD❐ Supports both 1.5 V and 1.8 V I/O supply

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement