MAX3782UTK+TD ADI DUAL 1.25Gbps Transceiver Integrated Circuits
MAX3782UTK+TD
,MAX3782UTK+TD Transceiver IC
,Transceiver Integrated Circuits
MAX3782UTK+TD ADI DUAL 1.25Gbps Transceiver Integrated Circuits
| Analog Devices Inc. | |
| Product Category: | ADI |
| Brand: | Analog Devices / Maxim Integrated |
| Series: | MAX3782 |
Description
The MAX3782 is a dual 1.25Gbps data retiming and clock recovery transceiver. It interfaces 1.25Gbps
LVDS data and clock to a 1.25Gbps serial interface compatible with 1000Base-SX/LX (IEEE 802.3z-2000)
standards, GBIC, and small form-factor pluggable (SFP) module interface recommendations. The serial
differential transmitter and receiver are PECL compatible using an ACcoupled CML interface with on-chip
termination/bias resistors for superior forward and back terminations. The transmit path converts the LVDS
signaling to CML and retimes the serial data to a low-jitter reference clock. The transmitter section contains
LVDS buffers, FIFO, clock multiplier, and CML output buffers. The transmitter accepts a single 1.25Gbps
serial-data channel and a 625MHz double-data-rate (DDR) clock that are compatible with IEEE Std
1596-1996 DC specifications. Serial LVDS data is clocked into the FIFO on both edges of the 625MHz
source-synchronous TCLK. Data is clocked out of the FIFO using an internal 1.25GHz clock derived from
a low-jitter 125MHz reference. Serial data is then clocked out as differential CML. The receive path converts
the CML signaling to LVDS and locks on to the data stream to recover the sourcesynchronous clock (RCLK).
The receive section contains a CML input buffer, clock recovery circuit, and LVDS output buffers. The receiver
accepts a CML serial data stream. The clock recovery phase-locked loop (PLL) locks on to the incoming
serial data stream and generates a 625MHz LVDS DDR clock. RCLK edges are at the center of the “eye”
of RDAT data.
