MPC8536ECVJAULA Microprocessor MPU Power QUICC 32 Bit Power Arch SoC
MPC8536ECVJAULA
,MPC8536ECVJAULA Microprocessor MPU
,32 Bit Microprocessor MPU
MPC8536ECVJAULA Microprocessors - MPU Power QUICC 32 Bit Power Arch SoC
| N-X-P | |
| Product Category: | Microprocessors - MPU |
| RoHS: | Details |
| e500 | |
| 1 Core | |
| 32 bit | |
| 1.333 GHz | |
| FC-PBGA-783 | |
| 32 kB | |
| 32 kB | |
| 1 V | |
| SMD/SMT | |
| - 40 C | |
| + 105 C | |
| Tray | |
| Brand: | N-X-P Semiconductors |
| I/O Voltage: | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Instruction Type: | Floating Point |
| Interface Type: | Ethernet, I2C, PCIe, SPI, UART, USB |
| L2 Cache Instruction / Data Memory: | 512 kB |
| Memory Type: | L1/L2 Cache |
| Number of Timers/Counters: | 1 Timer |
| Processor Series: | PowerQUICC III |
| Product Type: | Microprocessors - MPU |
| Subcategory: | Microprocessors - MPU |
| Watchdog Timers: | No Watchdog Timer |
| Part # Aliases: | 935320311557 |
| Unit Weight: | 0.132976 oz |
• High-performance, 32-bit e500 core, scaling up to1.5 GHz, that implements the Power
Architecture®technology
– 36-bit physical addressing
– Double-precision embedded floating point APU using64-bit operands
– Embedded vector and scalar single-precisionfloating-point APUs using 32- or 64-bit operands
– Memory management unit (MMU)
• Integrated L1/L2 cache
– L1 cache—32-Kbyte data and 32-Kbyte instruction
– L2 cache—512-Kbyte (8-way set associative)
• DDR2/DDR3 SDRAM memory controller with full ECCsupport– One 64-bit/32-bit data bus
– Up to 333-MHz clock (667-MHz data rate)
– Supporting up to 16 Gbytes of main memory
– Using ECC, detects and corrects all single-bit errors anddetects all double-bit errors and all errors
within a nibble
– Invoke a level of system power management byasserting MCKE SDRAM signal on-the-fly to put
thememory into a low-power sleep mode
– Both hardware and software options to supportbattery-backed main memory
• Integrated security engine (SEC) optimized to process allthe algorithms associated with IPsec, IKE,
SSL/TLS,iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.
– XOR engine for parity checking in RAID storageapplications
• Enhanced Serial peripheral interfaces (eSPI)– Support boot capability from eSPI
• Two enhanced three-speed Ethernet controllers (eTSECs)with SGMII support
– Three-speed support (10/100/1000 Mbps)
– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,IEEE 802.3z,
IEEE 802.3ac, IEEE 802.3ab, andIEEE Std 1588™-compatible controllers
– Support for various Ethernet physical interfaces: GMII,TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
– Support TCP/IP acceleration and QOS features
– MAC address recognition and RMON statistics support
– Support ARP parsing and generating wake-up eventsbased on the parsing results while in deep
sleep mode
– Support accepting and storing packets while in deepsleep mode
• High-speed interfaces (multiplexed) supporting:
– Three PCI Express interfaces
– PCI Express 1.0a compatible
– One x8/x4/x2/x1 PCI Express interface
– Two x4/x2/x1 ports, or,– One x4/x2/x1 port and Two x2/x1 ports
– Two SGMII interfaces– Two Serial ATA (SATA) controllers support SATA I andSATA I data rates
• PCI 2.2 compatible PCI controller
• Three universal serial bus (USB) dual-role controllerscomply with USB specification revision 2.0
• 133-MHz, 32-bit, enhanced local bus (eLBC) with memorycontroller
• Enhanced secured digital host controller (eSDHC) used forSD/MMC card interface– Support boot
capability from eSDHC
• Integrated four-channel DMA controller
• Dual I2C and dual universal asynchronousreceiver/transmitter (DUART) support
• Programmable interrupt controller (PIC)
• Power management, low standby power
– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
– PMC wake on: LAN activity, USB connection or remotewakeup, GPIO, internal timer, or external
interrupt event
• System performance monitor
• IEEE Std 1149.1™-compatible, JTAG boundary scan
• 783-pin FC-PBGA package, 29 mm × 29 mm
