9ZML1233EKILF Clock Buffer 9ZML1233E DB1200ZL MUX DERIV +WRTLK Integrated Circuits ICs
9ZML1233EKILF
,9ZML1233EKILF Clock Buffer IC
,Clock Buffer Integrated Circuits ICs
9ZML1233EKILF Clock Buffer 9ZML1233E DB1200ZL MUX DERIV +WRTLK
| IDT | |
| Product Category: | Clock Buffer |
| RoHS: | Details |
| 12 Output | |
| 3.6 ns | |
| HCSL | |
| VFQFPN-72 | |
| Differential | |
| 400 MHz | |
| 3.135 V | |
| 3.465 V | |
| 9ZML1233 | |
| - 40 C | |
| + 85 C | |
| Brand: | IDT |
| Duty Cycle - Max: | 55 % |
| Height: | 1 mm |
| Length: | 10 mm |
| Moisture Sensitive: | Yes |
| Mounting Style: | SMD/SMT |
| Operating Supply Current: | 22 mA |
| Packaging: | Tray |
| Product: | Clock Buffers |
| Product Type: | Clock Buffers |
| Subcategory: | Clock & Timer ICs |
| Type: | Low Phase Noise |
| Width: | 10 mm |
| Unit Weight: | 2.425891 oz |
Description
The 9ZML1233E/9ZML1253E are second generation enhancedperformance DB1200ZL derivatives.
The parts are pin-compatibleupgrades to the 9ZML1232B, while offering much improved phasejitter
performance. A fixed external feedback maintains low drift forcritical QPI/UPI applications, while each input
channel hassoftware adjustable input-to-output delay to ease transport delaymanagement for today's more
complex server topologies. The9ZML1233E and 9ZML1253E have an SMBus Write Lockout pinfor increased
device and system security.
Features
▪ SMBus write lock feature; increases system security
▪ 2 software-configurable input-to-output delay lines; managetransport delay for complex topologies
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area(1233E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save82mm2 of area (1253E)
▪ 12 OE# pins; hardware control of each output
▪ 3 selectable SMBus addresses; multiple devices can sharesame SMBus segment
▪ Selectable PLL bandwidths; minimizes jitter peaking incascaded PLL topologies
▪ Hardware/SMBus control of PLL bandwidth and bypass;change mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock forEMI reduction
▪ 100MHz PLL Mode; UPI support
▪ 10 x 10 mm 72-VFQFPN package; small board footprint
PCIe Clocking Architectures
▪ Common Clocked (CC)
▪ Independent Reference (IR) with and without spread spectrum
Typical Applications
▪ Servers
▪ Storage
▪ Networking
▪ SSDsOutput Features
▪ 12 Low-Power (LP) HCSL output pairs (1233E)
▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E)
Key Specifications
▪ Cycle-to-cycle jitter < 50ps
▪ Output-to-output skew < 50ps
▪ Input-to-output delay: 0ps default
▪ Input-to-output delay variation < 50ps
▪ Phase jitter: PCIe Gen4 < 0.5ps rms
▪ Phase jitter: UPI > 9.6GB/s < 0.1ps rms
▪ Phase jitter: IF-UPI < 1.0ps rms
