ZL40215LDG1 Clock Buffer 1:4 LVDS Fanout Buffer w/Int. Term. Integrated Circuits ICs
Clock Buffer Integrated Circuits ICs
,ZL40215LDG1 Clock Buffer
,ZL40215LDG1
ZL40215LDG1 Clock Buffer 1:4 LVDS Fanout Buffer w/Int. Term.
| Microchip | |
| Product Category: | Clock Buffer |
| RoHS: | Details |
| 4 Output | |
| 2 ns | |
| QFN-16 | |
| 750 MHz | |
| 2.375 V | |
| 3.465 V | |
| - 40 C | |
| + 85 C | |
| Brand: | Microchip Technology |
| Moisture Sensitive: | Yes |
| Mounting Style: | SMD/SMT |
| Packaging: | Tray |
| Product: | Fanout Buffers |
| Product Type: | Clock Buffers |
| Subcategory: | Clock & Timer ICs |
| Unit Weight: | 0.002014 oz |
Description
The ZL40215 is an LVDS clock fanout buffer with four identical output clock drivers capable of operating at frequencies up to 750MHz. The ZL40215 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40215 can accept DC or AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available. The ZL40215 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C. The device block diagram is shown in Figure 1; its operation is described in the following sections.
Features
Inputs/Outputs
• Accepts differential or single-ended input
• LVPECL, LVDS, CML, HCSL LVCMOS
• On-chip input termination resistors and biasing for AC coupled inputs
• Four precision LVDS outputs
• Operating frequency up to 750 MHz
Power
• Options for 2.5 V or 3.3 V power supply
• Current consumption of 62 mA
• On-chip Low Drop Out (LDO) Regulator for superior power supply rejection Performance
• Ultra low additive jitter of 78 fs RMS
Applications
• General purpose clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration
• Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC
• Wireless communications
• High performance micro-processor clock distribution
Tel: +86-755-23606019
Address: Room 1205-1207,Nanguang building,Huafu Road, Futian District,Shenzhen,Guangdong,China
Laneya
Telephone:+86-13420902155
E-mail:sales@wisdtech.com.cn
Wechat:laneyatao66
WhatsApp:+8613420902155
Skype:sales@wisdtech.com.cn
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