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AD6652BBCZ RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

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AD6652BBCZ RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs
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Introduction

AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

AD6652BBCZ RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

Analog Devices Inc.
Product Category: RF Receiver
RoHS:
+ 85 C
- 40 C
BGA-256
SMD/SMT
Tray
Brand: Analog Devices
Moisture Sensitive: Yes
Product Type: RF Receiver
Series: AD6652
Subcategory: Wireless & RF Integrated Circuits
Supply Voltage - Max: 2.5 V
Technology: Si
Unit Weight: 0.098203 oz

 

DESCRIPTION

The AD6652 is a mixed-signal IF to baseband receiverconsisting of dual 12-bit 65 MSPS ADCs and a widebandmultimode digital downconverter (DDC). The AD6652 isdesigned to support communications applications where lowcost, small size, and versatility are desired. The AD6652 is alsosuitable for other applications in imaging, medical ultrasound,instrumentation, and test equipment.

 

The dual ADC core features a multistage differential pipelinedarchitecture with integrated output error correction logic. BothADCs feature wide bandwidth differential sample-and-holdanalog input amplifiers supporting a variety of user-selectableinput ranges. An integrated voltage reference eases designconsiderations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing theconverters to maintain excellent performance.

 

ADC data outputs are internally connected directly to thereceiver’s digital downconverter (DDC) input matrix, simplifying layout and reducing interconnection parasitics. Overrangebits are provided for each ADC channel to alert the user toADC clipping. Level indicator bits are also provided for eachDDC input port that can be used for external digital VGAcontrol.

The digital receiver has four reconfigurable channels andprovides extraordinary processing flexibility. The receiver inputmatrix routes the ADC data to individual channels, or to all fourreceive processing channels. Each receive channel has fivecascaded signal processing stages: a 32-bit frequency translator(numerically controlled oscillator (NCO)), two fixed-coefficientdecimating filters (CIC), a programmable RAM coefficientdecimating FIR filter (RCF), and an interpolating half-bandfilter/AGC stage. Following the CIC filters, one, several, or allchannels can be configured to use one, several, or all the RCFfilters. This permits the processing power of four 160-tap RCFFIR filters to be combined or used individually.

 

After FIR filtering, data can be routed directly to the twoexternal 16-bit output ports. Alternatively, data can be routedthrough two additional half-band interpolation stages, where upto four channels can be combined (interleaved), interpolated,and processed by an automatic gain control (AGC) circuit with96 dB range. The outputs from the two AGC stages are alsorouted directly to the two external 16-bit output ports. Eachoutput port has a 16-bit parallel output and an 8-bit link port topermit seamless data interface with DSP devices such as theTS-101 TigerSHARC® DSP. A multiplexer for each port selectsone of six data sources to appear on the device outputs pins.

 

The AD6652 is part of the Analog Devices SoftCell® multimodeand multicarrier transceiver chipset. The SoftCell receiver digitizes a wide spectrum of IF frequencies and then downconverts the desired signals to baseband using individualchannel NCOs. The AD6652 provides user-configurable digitalfilters for removal of undesired baseband components, and thedata is then passed on to an external DSP, where demodulationand other signal processing tasks are performed to complete theinformation retrieval process. Each receive channel is independently configurable to provide simultaneous reception of thecarrier to which it is tuned. This IF sampling architecturegreatly reduces component cost and complexity compared withtraditional analog techniques or less integrated digital methods.

 

High dynamic range decimation filters offer a wide range ofdecimation rates. The RAM-based architecture allows easyreconfiguration for multimode applications. The decimatingfilters remove unwanted signals and noise from the channel ofinterest. When the channel occupies less bandwidth than theinput signal, this rejection of out-of-band noise is referred to asprocessing gain. By using large decimation factors, this processing gain can improve the SNR of the ADC by 20 dB or more. Inaddition, the programmable RAM coefficient filter allowsantialiasing, matched filtering, and static equalization functionsto be combined in a single, cost-effective filter.

 

Flexible power-down options allow significant power savings,when desired.

 

PRODUCT HIGHLIGHTS
Integrated dual 12-bit 65 MSPS ADC.
Integrated wideband digtal downconverter (DDC).
Proprietary, differential SHA input maintains excellent  SNR performance for input frequencies up to 200 MHz.
●Crossbar -switched digital downconverter input ports.
Digital resampling permits noninteger relationships between the ADC dock and the digital output data rate.
●Energy saving power down modes.

32-bit NCOs with selectable amplitude and phase dithering for better than -100 dBc spurious performance.
CIC filters with user- programmable decimation and interpolation factors.
160-tap RAM coefficient filter for each DDC channel.

Dual 16 bit parallel output ports and dual 8 -bit link ports.
●8-bit microport for register programming, register read- back, and coefficient memory programming.

 

 

FEATURES
SNR = 90 dB in 150 kHz bandwidth (to Nyquist@ 61.44 MSPS)

Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
Integrated dual-channel ADC:
Sample rates up to 65 MSPS
IF sampling frequencies to 200 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range(1 Vto 2 V p-p)
Differential analog inputs
ADC dlock duty cycle stabilizer
85 dB channel isolation/crosstalk


Integrated wideband digital downconverter (DDC):
Crossbar switched DDC inputs
Digital resampling for noninteger decimation
Programmable decimating FIR filters
Flexible control for multicarrier and phased array
Dual AGC stages for output level control
Dual 16-bit parallel or 8-bit link output ports
User-configurable built in self-test (BIST) capability
Energy-saving power-down modes

 

 

APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Instrumentation and test equipment

 

AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

 

 




AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

 

AD6652BBCZ  RF Receiver Dual Channel ADC with Quad Channel RSP Integrated Circuits ICs

Wisdtech Technology Co.,Limited
Tel: +86-755-23606019
Address: Room 1205-1207,Nanguang building,Huafu Road,
Futian District,Shenzhen,Guangdong,China

 

Laneya
Telephone:+86-13420902155
E-mail:sales@wisdtech.com.cn
Wechat:laneyatao66
WhatsApp:+8613420902155
Skype:sales@wisdtech.com.cn

 

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