LPC2388FBD144K ARM7 LPC2300 Microcontroller IC 16/32-Bit 72MHz 512KB (512K x 8) FLASH

LPC2388FBD144K ARM7 LPC2300 Microcontroller IC 16/32-Bit 72MHz 512KB

(512K x 8) FLASH

Description

The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU withreal-time emulation that

combines the microcontroller with 512 kB of embeddedhigh-speed flash memory. A 128-bit wide memory

interface and a unique acceleratorarchitecture enable 32-bit code execution at the maximum clock rate.

For criticalperformance in interrupt service routines and DSP algorithms, this increases performanceup to

30 % over Thumb mode. For critical code size applications, the alternative 16-bitThumb mode reduces

code by more than 30 % with minimal performance penalty.The LPC2388 is ideal for multi-purpose serial

communication applications. It incorporatesa 10/100 Ethernet Media Access Controller (MAC), USB

device/host/OTG with 4 kB ofendpoint RAM, four UARTs, two CAN channels, an SPI interface, two

Synchronous SerialPorts (SSP), three I2C-bus interfaces, an I2S-bus interface, and an External Memory

Controller (EMC). This blend of serial communications interfaces combined with anon-chip 4 MHz internal

oscillator, SRAM of 64 kB, 16 kB SRAM for Ethernet, 16 kB SRAMfor USB and general purpose use,

together with 2 kB battery powered SRAM make thisdevice very well suited for communication gateways

and protocol converters. Various32-bit timers, an improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN

control unit, and upto 104 fast GPIO lines with up to 50 edge and up to four level sensitive external

interruptpins make these microcontrollers particularly suitable for industrial control and medicalsystems.

Features

• ARM7TDMI-S processor, running at up to 72 MHz.
•  Up to 512 kB on-chip flash program memory with In-System Programming (ISP) andIn-Application Programming (IAP) capabilities. Flash program memory is on the ARMlocal bus for high performance CPU access.
•  64 kB of SRAM on the ARM local bus for high performance CPU access.
•  16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
•  16 kB SRAM for general purpose DMA use also accessible by the USB.
•  Dual Advanced High-performance Bus (AHB) system that provides for simultaneousEthernet DMA, USB DMA, and program execution from on-chip flash with nocontention between those functions. A bus bridge allows the Ethernet DMA to accessthe other AHB subsystem.
•  EMC provides support for static devices such as flash and SRAM as well as off-chipmemory mapped peripherals.
•  Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts
•  General Purpose DMA controller (GPDMA) on AHB that can be used with the SSPserial interfaces, the I2S-bus port, and the Secure Digital/MultiMediaCard (SD/MMC)card port, as well as for memory-to-memory transfers.
•  Serial Interfaces:
•  Ethernet MAC with associated DMA controller. These functions reside on anindependent AHB.
•  USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller.
•  Four UARTs with fractional baud rate generation, one with modem control I/O, onewith IrDA support, all with FIFO.
•  CAN controller with two channels.
•  SPI controller.
•  Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternatefor the SPI port, sharing its interrupt and pins. These can be used with the GPDMAcontroller.
•  Three I2C-bus interfaces (one with open-drain and two with standard port pins).
•  I2S (Inter-IC Sound) interface for digital audio input or output. It can be used withthe GPDMA.
•  Other peripherals: SD/MMC memory card interface.
•  104 General purpose I/O pins with configurable pull-up/down resistors.
•  10-bit ADC with input multiplexing among 8 pins.
• 10-bit DAC.
•  Four general purpose timers/counters with 8 capture inputs and 10 compareoutputs. Each timer block has an external count input.
•  One PWM/timer block with support for three-phase motor control. The PWM hastwo external count inputs.
•  Real-Time Clock (RTC) with separate power pin, clock source can be the RTCoscillator or the APB clock.
•  2 kB SRAM powered from the RTC power pin, allowing data to be stored when therest of the chip is powered off.
•  WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,the RTC oscillator, or the APB clock.
•  Standard ARM test/debug interface for compatibility with existing tools.
•  Emulation trace module supports real-time trace.
•  Single 3.3 V power supply (3.0 V to 3.6 V). Four reduced power modes: Idle, Sleep, Power-down and Deep power-down.
•  Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0and Port 2 can be used as edge sensitive interrupt sources.
•  Processor wake-up from Power-down mode via any interrupt able to operate duringPower-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernetwake-up interrupt).
• Two independent power domains allow fine tuning of power consumption based onneeded features.
•  Each peripheral has its own clock divider for further power saving.
•  Brownout detect with separate thresholds for interrupt and forced reset.
•  On-chip power-on reset.
•  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz